AI2EDGE: Combining ultra-fast Virtual Platforms with state-of-the-art AI Compilers
AI on the edge is moving fast—and that speed is both an opportunity and a problem. In this post, we introduce AI2EDGE, a publicly funded project supported by the European Union and the Ministerium für Wirtschaft, Industrie, Klimaschutz und Energie des Landes Nordrhein-Westfalen (MWIKE). The project brings together compiler technology and virtual platforms to make it easier to evaluate and deploy AI workloads on constrained, heterogeneous hardware. Before diving into the “how”, it’s worth clarifying the “why”: edge AI deployment is still too hard, too slow, and too dependent on having the right hardware on your desk.
The Pain of Edge AI
Training an AI model is only half the job. The other half — getting it to run reliably and efficiently on the target device — often consumes the most time.
In practice, teams face a fragmented ecosystem: different frameworks and model formats (e.g., TensorFlow, Caffe, Apache TVM), rapidly changing toolchains, and inevitable incompatibilities. Some approaches age out quickly, leaving behind abandoned conversion scripts and brittle pipelines.
On edge devices (phones, embedded Linux systems, microcontrollers), the constraints are harsher: limited memory, limited compute, strict power budgets, and a smaller software stack. Even if you manage to get a model running, performance and efficiency can still be far from production-ready.
This is where compiler toolchain of our partner Roofline AI comes into play: it helps bridge the gap between models and diverse hardware targets by turning AI workloads into efficient implementations for the chosen platform.
The Need for Virtual Platforms
Compiler support alone doesn’t remove a major real-world bottleneck: hardware availability.
Many companies evaluate multiple chips and acceleration options in parallel. But physical prototypes are often scarce, arrive late, or are shared among many teams. That makes early software bring-up, performance exploration, and regression testing difficult.
MachineWare addresses this with Virtual Platforms (VPs). A VP simulates a complete microprocessor-based system on a general-purpose computer. For example, the following VP includes a RISC-V CPU model, peripherals, and a Neural Processing Unit (NPU):
When done well, software developers can work against a VP with the same workflows they would use on real hardware—often long before physical devices are broadly available. Because it’s software, a VP can also be cloned, versioned, and integrated into CI/CD for repeatable regression testing.
Within AI2EDGE, MachineWare contributes their SIM-V instruction-set simulator for CPU simulation and their open-source peripheral modeling library VCML.
Combining Virtual Platforms and AI Compilers
AI2EDGE combines these two worlds: Roofline’s compilation technology and MachineWare’s simulation technology. The goal is a workflow where teams can answer questions like: “Can my model run on chip X—and what performance should I expect?” …quickly and repeatedly, without needing physical prototypes. This enables rapid iteration across hardware options and reduces risk when selecting a target platform. Use cases and requirements are defined together with Fraunhofer IPT. Overall, the project aims to deliver an integrated system along the following lines:
If you’re working on edge AI deployment and want to reduce the friction between “model trained” and “model running on target hardware,” AI2EDGE is all about closing that gap—by pairing robust compilation with realistic, automation-friendly virtual platforms.
